The Parasitic Extraction tool is used by netlisters and other parts of the system that need to know about geometric factors. To control Parasitic Extraction, use the "Parasitic" preferences (in menu File / Preferences..., "Tools" section, "Parasitic" tab).

Each layer of every technology is listed, and you can set its unit resistance, area capacitance, and edge capacitance. The "Factory Reset" buttons reverts values to the default shipped with Electric.

The middle section controls values for every layer in a technology. You can set the minimum resistance and capacitance, as well as the maximum series resistance. The maximum series resistance breaks long single PI models into series of distributed PI models. "Include Gate In Resistance" requests that a transistor's gate area be included in overall area calculations for resistance determination. "Include Ground Network" requests that ground networks be analyzed. The "Gate Length Shrink" is a compensation factor for gate lengths. Some process technologies shrink the gate length by a fixed amount.

The bottom part of the technology offers more controls:

- "Use Verbose Naming" The parasitic extractor inserts resistors, and thus makes multiple networks out of a single network. The new networks are automatically named by the netlister. Normally, the names are simple, such as "oldnetworkname#1". When verbose naming is requested, the network names include the nodes to which they connect, for example "oldnetworkname#m1m2conn-conn@0". This makes it possible for the user to cross-probe back to the layout from the expanded Spice file, but it makes the file larger.
- "Back Annotate Layout" transfers schematic net names to layout net names after NCC completes and matches. This allows one to probe networks in layout with the same name as in the schematics, making it easier to compare schematic simulations against layout simulations.