Electric can produce input decks for Verilog simulation with Write Verilog Deck... command (in menu Tool / Simulation (Verilog)). After this has been done, you must run Verilog externally to produce a ".dump" file. Note that the Electric distribution does not come with a Verilog simulator: you must obtain it separately.

After running a Verilog simulation, you can read the ".dump" file into Electric and display it in a waveform window. This is done with the Plot Verilog VCD Dump... command (in menu Tool / Simulation (Verilog)). You can also use the Plot Verilog for This Cell command if the cell name and file name are the same. The Verilog simulation information is then shown in a digital waveform window (see Section 4-11-1 for more). Electric also understands the output of Modelsim and can plot it.

Before generating Verilog decks, it is possible to annotate circuits with additional Verilog declarations and code that will be included in the deck. To add Verilog code, select "Verilog Code" under the "Misc." entry in the component menu of the side bar. To add a Verilog declaration, select "Verilog Declaration" under the "Misc." entry in the component menu. These pieces of text can be manipulated like any other text object (see Section 6-8-1 on text). For an example of Verilog layout and code, look at the cell "tool-SimulateVERILOG" in the Samples library (get this library with the Sample Cells command, in menu Help / Load Built-in Libraries).

Additional control of Verilog deck generation is accomplished with the Verilog Project Settings (in menu File / Project Settings..., "Verilog" tab). A checkbox lets you choose whether or not to use the Verilog "assign" construct. You can control the type of Verilog declaration that will be used for wires ("wire" by default, "trireg" if checked). Note that this can be overridden with the Set Verilog Wire command (in menu Tool / Simulation (Verilog)).

Another property that can be assigned to transistors is their strength. The Weak command (in menu Tool / Simulation (Verilog) / Transistor Strength) sets the transistor to be weak. The Normal command restores the transistor to be normal strength.

Additional Verilog settings can be found in the Verilog Model Files Preferences (in menu File / Preferences..., "Tools" section, "Verilog Model Files" tab). For the difference between Preferences and Project Settings, see Section 6-3. |

The Verilog Model Files Preferences dialog lets you attach disk files with Verilog code to any cell in the library. Once attached, the generated Verilog will use the contents of that file instead of examining the cell contents. This allows you to create your own definitions in situations where the derived Verilog would be too complex or otherwise incorrect.