For both Spice and Verilog, you can create special nodes that augment the genetated deck. Spice even has a predefined set of primitives, available from the "Spice" entry in the component palette.

Users can define their own Spice or Verilog elements by creating new icons in this or a new library. The icon should have graphics, exports, optional parameters, and a template. Parameters are created with the Attribute Properties... command (in menu Edit / Attributes ). See Section 6-8-6 for more on parameters. The Spice template is created with the Set Generic Spice Template command (in menu Tool / Simulation (Spice)). If the template is specific to a particular version of Spice, use the appropriate template command (Set Spice 2 Template, Set Spice 3 Template, Set HSpice Template, Set PSpice Template, Set GnuCap Template, or Set SmartSpice Template).

You can also create Verilog elements by using the Set Verilog Template command (in menu Tool / Simulation (Verilog)). Note that a single cell can contain both Verilog and multiple Spice templates.

To explain the format of a template, a DC Voltage Source primitive is used as an example. Graphics is placed to describe the look of the symbol (a "battery" look). Exports are created at the top and bottom of the battery with the names "plus" and "minus". A single parameter is defined called "Voltage" with a default value of "0V". Finally, a Spice template is created that has the string
`V$(node_name) $(plus) $(minus) DC $(Voltage)`

This string contains substitution expressions of the form `$(SOMETHING)` where `SOMETHING` can be an export name, a variable, or "node_name". So, in this example, `$(node_name)` will be replaced with the name of the voltage node; `$(plus)` will be replaced with the net name attached to the positive terminal; and `$(Voltage)` will be replaced with the voltage value specified by the user.

The set of Spice primitives in Electric is useful, but far from complete. A second set, called "SpicePartsS3", is tailored towards special Spice3 primitives. There are no Verilog primitives in the current release of Electric. Users who define new primitives are encouraged to share these with the entire community by contacting Static Free Software.