<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Xga configuration</TITLE>
</HEAD>
<BODY BGCOLOR="#efefef" TEXT="black" LINK="blue" VLINK="#551A8B" ALINK="red">

<A HREF="agx.html"><EM>Notes on the AGX Server</EM></A>
 <b>:</b> <EM>Xga configuration</EM><BR>
<b>Previous:</b> <A HREF="agx5.html"><EM>XF86Config</EM></A><BR>
<b>Next:</b> <A HREF="agx.html"><EM>Notes on the AGX Server</EM></A>


<HR NOSHADE>
  <H2><A NAME="6"></A>6. Xga configuration</H2>



<p>          This server now has tested support for XGA-2 compatible 
boards (aka. XGA-NI). The main issue for XGA-1 support is 
whether clock probing works. At this time probing for board 
configuration is limited and detailed configuration may need to be 
done manually. </p>

<p>       By default the ISA POS register will be performed. If the
XGA Instance number is specified the scope of probing will
be narrowed a bit. To override or disable probing, a minimum
of the Instance, COPbase, and MEMbase must be specified
in the XF86Config device section for the XGA card. MCA 
probing is not supported.</p>

<p>
<dl>
<dt><b>Instance       nn</b><dd><p>XGA instance number (0-7).</p>

<dt><b>IObase        nnnn</b><dd><p>The I/O address of the the XGA
general control registers. The
standard, and default, is 0x21i0,
where i is the instance number.</p>

<dt><b>MEMbase        nnnn</b><dd><p>The XGA display memory address (the
address the XGA coprocessor uses
for video memory). This is also  
the system memory address of the
linear aperture on boards that
support it.</p>
<p>POS register 4 bits 7-1 contains
bits 31-25 of the XGA's display
memory address. Bits 24-22 of
of the display memory address
contains the XGA instance number.
Bit 0 of POS register 4 is not
used by this server as the XGA's
linear aperture is not used.
However, the coprocessor must 
still be configured with this.</p>
<p>The AGX-01[456]
chips have a fixed 
display memory address.</p>

<dt><b>COPbase     nnnnnn</b><dd><p>Address of the graphics engine's
memory mapped control registers.</p>
<p>Typically: </p>
<p>0xC1C00 + (ext_mem_addr * 0x2000)
+ (instance * 0x80)</p>
<p>where ext_mem_addr is the high
order 4-bits of POS register 2
(0-16 the server assumes zero).</p>
<p>The AGX-01[456] chips support 
0xB1F00 (default) and 0xD1F00.</p>

<dt><b>BIOSbase     nnnnnn</b><dd><p>Address of the XGA BIOS (not VGA BIOS).
Can be specified as an alternate to COPbase.</p>
<p>Typically: </p>
<p>0xC0000 + (ext_mem_addr * 0x2000)</p>
<p>where ext_mem_addr is the high
order 4-bits of POS register 2
(0-16 -- the server assumes zero).</p>

<dt><b>VGAbase        nnnn</b><dd><p>Can be used to override the default 0xA0000 
address for the 64KB video memory
address used by the server. The
only values acceptable are 0xA0000
and 0xB0000. VGA text mode restore
does not work under Linux if 0xB0000
is specified. </p>
<p>AGX-01[456]
also default to 0xA0000.</p>

<dt><b>POSbase       nnnn</b><dd><p>Can be used to specify an alternate POS register
probe address base from the ISA  
default of 0x100. The VESA VXE
standard for EISA is 0xzC80, where 
z is the slot number).</p>
<p>A value of zero will disable POS 
register probing (required for MCA). </p>

<dt><b>DACspeed      nnnn</b><dd><p>Can be used to override the servers default
maximum Pixel Clock for XGA-2 of 80Mhz. 
The limit can be raised as high as 90Mhz,
or set to lower values.</p>

</dl>
</p>
<p>        An alternate way to determine the POS register values is
with the setup/diag programs that should have been included
with your video board, or possibly from jumper values.</p>
<p>          
The XGA-2 has programmable clocks up to 90MHz, however
at 1024x768, 72MHz is generally the max that will produce
a stable display with the CatsEye/XGA-2 used for testing
(IBM coprocessor and INMOS RAMDAC/serializer). Higher clocks 
will often generate artifacts at the top and left edges of 
the screen. Such artifacts can sometimes be tuned out by
increasing the vertical and horizontal blanking intervals
or slightly changing the clock. At pixel clock rates above 
80Mhz I have seen the chip lose sync after running for several
minutes, so 80Mhz has been set as the default limit for XGA-2
pixel clocks. I don't have specs on actual limits, and as 
there are a number of different XGA chipsets, you should use 
the modes documented in your owner's manual as a guide to 
max refresh rates. No clocks or clockchip parm are required 
to specify use of programmable clocks for the XGA-2. </p>
<p>8bpp and 16bpp are supported for the XGA-2.</p>
<p>For XGA-1 cards the clocks must be specified as for
the AGX chips, it is not known whether the clockprobing
will work. Some XGA-1 chips may support 16bpp. </p>

<p>
<pre>
$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/agx.sgml,v 3.19.2.1 1998/11/07 13:37:50 dawes Exp $





$XConsortium: agx.sgml /main/9 1996/10/19 18:03:50 kaleb $
</pre>
</p>

 <HR NOSHADE>
<A HREF="agx.html"><EM>Notes on the AGX Server</EM></A>
 <b>:</b> <EM>Xga configuration</EM><BR>
<b>Previous:</b> <A HREF="agx5.html"><EM>XF86Config</EM></A><BR>
<b>Next:</b> <A HREF="agx.html"><EM>Notes on the AGX Server</EM></A>



</BODY>
</HTML>
