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<A HREF="S3.html"><EM> Information for S3 Chipset Users</EM></A>
 <b>:</b> <EM>Supported hardware</EM><BR>
<b>Previous:</b> <A HREF="S3.html"><EM> Information for S3 Chipset Users</EM></A><BR>
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<HR NOSHADE>
  <H2><A NAME="1"></A>1. Supported hardware</H2>
<p>The current S3 Server supports the following S3 chipsets: 911, 924,
801/805, 928, 732 (Trio32), 764, 765, 775, 785 (Trio64*), 
864, 868, 964, 968 and M65 (Aurora64V+).  The 
S3 server will also recognise the 866, but it has not been tested with
this chipset.  If you have any problems or success with these, please
report it to us.</p>
<p>Nevertheless, this is not enough to support every board using one of these
chipsets. The following list contains some data points on boards that are
known to work.  If your card is similar to one of the described ones,
chances are good it might work for you, too.</p>
<p>
<dl>
<dt><b>S3 801/805, AT&amp;T 20C490 (or similar) RAMDAC</b><dd><p>
<ul>
<li>Orchid Fahrenheit 1280+ VLB</li>
<li>Actix GE32</li>
</ul>
</p>
<p>8 and 15/16 bpp</p>
<p>Note: Real AT&amp;T20C490 RAMDACs should be automatically detected by
the server.  For others which are compatible, you need to provide
a `<code>Ramdac "att20c490"</code>'
entry in your <code>XF86Config</code>.</p>
<p>Real AT&amp;T 20C490 or 20C491 RAMDACs work with the
<code>"dac_8_bit"</code> option.  Some clones (like the Winbond
82C490) do not.</p>
<p>The Orchid Fahrenheit 1280+ VLB may require `<code>Option "nolinear"</code>'.</p>



<dt><b>S3 805 VLB, S3 GENDAC (RAMDAC + clock synthesizer)</b><dd><p>
<ul>
<li>MIRO 10SD (available for VLB and PCI)
It is not known whether all 10SDs use the S3 GENDAC.</li>
</ul>
</p>
<p>8 and 15/16 bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "s3gendac"
 RamDac    "s3gendac"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 801/805, AT&amp;T 20C490 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>STB PowerGraph X.24 S3 (ISA)</li>
</ul>
</p>
<p>8 and 15/16 bpp</p>
<p>Note: Real AT&amp;T20C490 RAMDACs should be automatically detected by
the server.  For others which are compatible, you need to provide
a `<code>Ramdac "att20c490"</code>'
entry in your <code>XF86Config</code>.</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 RamDac    "att20c490"
 Option    "dac_8_bit
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 805, Diamond SS2410 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>Diamond Stealth 24 VLB</li>
</ul>
 </p>
<p>8 and 15bpp(*) only.</p>
<p>requires `<code>Option "nolinear"</code>'</p>
<p>(*) The SS2410 RAMDAC is reportedly compatible with the AT&amp;T20C490
in 15bpp mode.  To make the server treat it as an AT&amp;T20C490,
you need to provide a `<code>Ramdac "att20c490"</code>' entry in your
<code>XF86Config</code>.</p>


<dt><b>S3 801/805, Chrontel 8391 Clockchip/Ramdac</b><dd><p>
<ul>
<li>JAX 8241</li>
<li>SPEA Mirage</li>
</ul>
 </p>
<p>8 and 15/16 bpp.</p>
<p>The 8391 is compatible with the AT&amp;T 20C490 RAMDAC</p>
<p>
<blockquote><code>
<pre>
 ClockChip "ch8391"
 Ramdac    "ch8391"
 Option    "dac_8_bit"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 928, AT&amp;T 20C490 RAMDAC </b><dd><p>
<ul>
<li>Actix Ultra</li>
</ul>
</p>
<p>8 and 15/16 bpp</p>
<p>Note: Real AT&amp;T20C490 RAMDACs should be automatically detected by
the server.  For others which are compatible, you need to provide
a `<code>Ramdac "att20c490"</code>'
entry in your <code>XF86Config</code>.  Also, the server's RAMDAC probe
reportedly causes problems with some of these boards, and a
RamDac entry should be used to avoid the probe.</p>
<p>Real AT&amp;T 20C490 or 20C491 RAMDACs work with the
<code>"dac_8_bit"</code> option.  Some clones (like the Winbond
82C490) do not.</p>


<dt><b>S3 928, Sierra SC15025 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>ELSA Winner 1000 ISA/EISA (``TwinBus'', not Winner1000ISA!!)</li>
<li>ELSA Winner 1000 VL</li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>Supports 8bit/pixel RGB in 8bpp and gamma correction for 15/16
and 24bpp modes</p>
<p>24 bpp might get ``snowy'' if the clock is near the limit of
30MHz. This is not considered dangerous, but limits the
usability of 24 bpp.</p>
<p>D-step (or below) chips cannot be used with a line width of
1152; hence the most effective mode for a 1 MB board is about
1088x800x8 (similar to 2 MB, 1088x800x16).</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 928, Bt9485 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>STB Pegasus VL </li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>Supports RGB with sync-on-green if <code>"sync_on_green"</code>
option is provided and board jumper is set for BNC outputs.</p>
<p>VLB linear addressing now occurs at 0x7FCxxxxx so that 64MB
or more main memory can be supported without losing linear
frame buffer access.</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 Option    "stb_pegasus"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 928, Bt485 RAMDAC, SC11412 Clockchip</b><dd><p>
<ul>
<li>SPEA Mercury 2MB VL</li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp   </p>
<p>
<blockquote><code>
<pre>
 ClockChip "SC11412"
 Option    "SPEA_Mercury"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 928, Bt485 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>#9 GXE Level 10, 11, 12</li>
</ul>
	</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 Option    "number_nine"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 928, Ti3020 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>#9 GXE Level 14, 16</li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>Supports RGB with sync-on-green</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 Option    "number_nine"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 864, AT&amp;T20C498, ICS2494 Clockchip</b><dd><p>
<ul>
<li>MIRO 20SD (BIOS 1.xx)</li>
</ul>
</p>
<p>The ICS2494 is a fixed frequency clockchip, you have to use
X -probeonly (without a Clocks line in XF86Config) to get the 
correct clock values.</p>
<p>8, 15/16 and 24(32) bpp</p>


<dt><b>S3 864, AT&amp;T20C498 or STG1700 RAMDAC, ICD2061A or ICS9161 Clockchip</b><dd><p>
<ul>
<li>Elsa Winner1000PRO VLB</li>
<li>Elsa Winner1000PRO PCI</li>
<li>MIRO 20SD (BIOS 2.xx)</li>
<li>Actix GraphicsENGINE 64 VLB/2MB</li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 864, 20C498 or 21C498 RAMDAC, ICS2595 Clockchip</b><dd><p>
<ul>
<li>SPEA MirageP64 2MB DRAM  (BIOS 3.xx)</li>
</ul>
</p>
<p>8, 15/16 and 24(32) bpp</p>
<p>Clockchip support is still sometimes flaky and on some machines
problems with the first mode after startup of XF86_S3 or after
switching back from VT have been seen; switching to next mode
with CTRL+ALT+``KP+'' and back seems to solve this problem.</p>
<p>Interlaced modes don't work correctly.</p>
<p>Mirage P64 with BIOS 4.xx uses the S3 SDAC.  </p>
<p>
<blockquote><code>
<pre>
 ClockChip "ics2595"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 864, S3 86C716 SDAC RAMDAC and Clockchip</b><dd><p>
<ul>
<li>Elsa Winner1000PRO</li>
<li>MIRO 20SD (BIOS 3.xx)</li>
<li>SPEA MirageP64 2MB DRAM  (BIOS 4.xx)</li>
<li>Diamond Stealth 64 DRAM</li>
</ul>
</p>
<p>8, 15/16 and 24 bpp</p>


<dt><b>S3 864, ICS5342 RAMDAC and Clockchip</b><dd><p>
<ul>
<li>Diamond Stealth 64 DRAM (only some cards)</li>
</ul>
</p>
<p>8, 15/16 and 24 bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "ics5342"
 Ramdac    "ics5342"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 864, AT&amp;T21C498-13 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>#9 GXE64 - PCI</li>
</ul>
</p>
<p>8, 15/16, 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 Option    "number_nine"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 964, AT&amp;T 20C505 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>Miro Crystal 20SV</li>
</ul>
</p>
<p>8, 15/16, 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 Ramdac    "att20c505"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 964, Bt485 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>Diamond Stealth 64</li>
</ul>
</p>
<p>8, 15/16, 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 964, Bt9485 or AT&amp;T 20C505 RAMDAC, ICS9161a Clockchip</b><dd><p>
<ul>
<li>SPEA Mercury 64</li>
</ul>
</p>
<p>8, 15/16, 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "ics9161a"
 Option    "SPEA_Mercury"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 964, Ti3020 RAMDAC, ICD2061A Clockchip</b><dd><p>
<ul>
<li>Elsa Winner2000PRO PCI</li>
</ul>
</p>
<p>8, 15/16, 24(32) bpp</p>
<p>
<blockquote><code>
<pre>
 ClockChip "icd2061a"
 
</pre>
</code></blockquote>
</p>


<dt><b>S3 964, Ti3025 RAMDAC, Ti3025 Clockchip</b><dd><p>
<ul>
<li>Miro Crystal 40SV</li>
<li>#9 GXE64 Pro VLB</li>
<li>#9 GXE64 Pro PCI</li>
</ul>
</p>
<p>8 bpp, 15, 16 and 24(32) bpp</p>
<p>There are some known problems with the GXE64 Pro support,
including some image shifting/wrapping at 15/16/24 bpp.</p>
<p>We have found that #9 no longer support the GXE64 Pro
at 1600x1200.  They do however have a new (and more expensive)
board called the GXE64Pro-1600 which uses a 220MHz RAMDAC
instead of 135MHz part used on the other boards.</p>


<dt><b>S3 764 (Trio64)</b><dd><p>
<ul>
<li>SPEA Mirage P64 (BIOS 5.xx)</li>
<li>Diamond Stealth 64 DRAM</li>
<li>#9 GXE64 Trio64</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>
<p>Note: The Trio64 has a builtin RAMDAC and clockchip, so the server
should work with all Trio64 cards, and there is no need to specify
the RAMDAC or clockchip in the <code>XF86Config</code> file.</p>


<dt><b>S3 732 (Trio32)</b><dd><p>
<ul>
<li>Diamond Stealth 64 DRAM SE</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>
<p>Note: The Trio32 has a builtin RAMDAC and clockchip, so the server
should work with all Trio32 cards, and there is no need to specify
the RAMDAC or clockchip in the <code>XF86Config</code> file.</p>


<dt><b>S3 868, S3 86C716 SDAC RAMDAC and Clockchip</b><dd><p>
<ul>
<li>ELSA Winner 1000AVI</li>
<li>Diamond Stealth Video DRAM</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>

<dt><b>S3 868, AT&amp;T 20C409 RAMDAC and Clockchip</b><dd><p>
<ul>
<li>ELSA Winner 1000AVI</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>
<p>Note: pixelmultiplexing is not supported yet, therefore limited
maximum dot clock for 8bpp (currently 67.5MHz, should be changed
to 100MHz if pixmux isn't fixed prior to release)</p>

<dt><b>S3 968, Ti3026 RAMDAC, Ti3026 Clockchip</b><dd><p>
<ul>
<li>Elsa Winner 2000PRO/X-2 and /X-4 (Revsions &lt;= F)</li>
<li>Elsa Winner 2000AVI-2 and -4 </li>
<li>Diamond Stealth 64 VIDEO VRAM </li>
</ul>
</p>
<p>8/15/16/24 bpp</p>

<dt><b>S3 968, Ti3026 RAMDAC, ICS9161A Clockchip</b><dd><p>
<ul>
<li>Elsa Winner 2000PRO/X-2 and /X-4 (Revision G)</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>
<p>Note: clock doubling doesn't work, yet, therefore the maximum
usable dot clock is limited to about 120MHz.</p>

<dt><b>S3 964, IBM RGB 514/524/525/528 RAMDAC &amp; Clockchip</b><dd><p>
<ul>
<li>Hercules Graphics Terminator 64</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>
<p>
<blockquote><code>
<pre>
 s3RefClk   50
 DACspeed  170
 Option  "slow_vram"
 
</pre>
</code></blockquote>
</p>

<dt><b>S3 968, IBM RGB 514/524/525/528 RAMDAC &amp; Clockchip</b><dd><p>
<ul>
<li>Genoa Genoa VideoBlitz III AV
<blockquote><code>
<pre>
 s3RefClk   50
 DACspeed  170
 
</pre>
</code></blockquote>
</li>
<li>Hercules Graphics Terminator Pro 64
<blockquote><code>
<pre>
 s3RefClk   16
 DACspeed  220
 
</pre>
</code></blockquote>

This card may require the line:
<blockquote><code>
<pre>
        Invert_VCLK "*" 0
 
</pre>
</code></blockquote>

in each Display subsection.</li>
<li>STB Velocity 64
<blockquote><code>
<pre>
 s3RefClk   24
 DACspeed  220
 
</pre>
</code></blockquote>
</li>
<li>Number Nine FX Motion 771
<blockquote><code>
<pre>
 s3RefClk   16
 DACspeed  220
 
</pre>
</code></blockquote>

This card may require the line:
<blockquote><code>
<pre>
 Invert_VCLK "*" 0
 
</pre>
</code></blockquote>

in each Display subsection.</li>
<li>MIRO 80SV
<blockquote><code>
<pre>
 s3RefClk   16
 DACspeed  250
 
</pre>
</code></blockquote>
</li>
</ul>
</p>
<p>8/15/16/24 bpp</p>

<dt><b>ELSA Winner 2000PRO/X-8 (S3 968, 8MB VRAM, 220MHz for 32bpp)</b><dd><p>The server has only been tested for "revision C" of this card
(guess the serial number should start with C, but not sure since
mine says  Ser.No. A-0000.000.000;)  which have an IBM RGB528A
note the A;  can't be probed though)</p>
<p>depending on the mode line etc there may be some display distortions like:
<ol>
<li>many long horizontal lines/stripes</li>
<li>pixel jitter or short horizontal stripes like snow all over the
screen</li>
<li>Like 2., but only when doing graphics ops (like opaque move of
windows).</li>
<li>additional pixel at the left display edge and some missing pixels
at the right edge.</li>
</ol>

All of these problems can be fixed by small adjustments to the mode line
(best to run `xvidtune' and make these adjustments interactively).  E.g.,
for the first three problems, shift the display left or right a few steps.
For the last problem, increasing HSyncEnd (making the hsync pulse longer)
solves the problem.  In some cases, a significant increase in the sync
pulse width is needed, and rarely, it needs to be shortened (by decreasing
HSyncEnd).</p>
<p>In rare cases, InvertVCLK and/or EarlySC may need to be adjusted, followed
by an adjustment of BlankDelay (see the bottom line of xvidtune).</p>
<p>If you see any of these problems, please contact
<A href="mailto:koenig@XFree86.org">koenig@XFree86.org</A>, and
send details of:
<ul>
<li>Original mode showing the problem,</li>
<li>Tuned/fixed mode, including all flags from the bottom line of
xvidtune,</li>
<li>Colour depth used for this tuned mode line,</li>
<li>Full server startup output.</li>
</ul>
</p>


</dl>
</p>

 <HR NOSHADE>
<A HREF="S3.html"><EM> Information for S3 Chipset Users</EM></A>
 <b>:</b> <EM>Supported hardware</EM><BR>
<b>Previous:</b> <A HREF="S3.html"><EM> Information for S3 Chipset Users</EM></A><BR>
<b>Next:</b> <A HREF="S32.html"><EM>16bpp and 32bpp</EM></A>



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