   This file documents the GNU Assembler "as".

   Copyright (C) 1991, 1992, 1993 Free Software Foundation, Inc.

   Permission is granted to make and distribute verbatim copies of this
manual provided the copyright notice and this permission notice are
preserved on all copies.

   Permission is granted to copy and distribute modified versions of
this manual under the conditions for verbatim copying, provided also
that the section entitled "GNU General Public License" is included
exactly as in the original, and provided that the entire resulting
derived work is distributed under the terms of a permission notice
identical to this one.

   Permission is granted to copy and distribute translations of this
manual into another language, under the above conditions for modified
versions, except that the section entitled "GNU General Public License"
may be included in a translation approved by the Free Software
Foundation instead of in the original English.

Register Names
..............

   General-purpose registers are represented by predefined symbols of
the form `GRNNN' (for global registers) or `LRNNN' (for local
registers), where NNN represents a number between `0' and `127',
written with no leading zeros.  The leading letters may be in either
upper or lower case; for example, `gr13' and `LR7' are both valid
register names.

   You may also refer to general-purpose registers by specifying the
register number as the result of an expression (prefixed with `%%' to
flag the expression as a register number):
     %%EXPRESSION

--where EXPRESSION must be an absolute expression evaluating to a
number between `0' and `255'.  The range [0, 127] refers to global
registers, and the range [128, 255] to local registers.

   In addition, `as' understands the following protected
special-purpose register names for the AMD 29K family:

       vab    chd    pc0
       ops    chc    pc1
       cps    rbp    pc2
       cfg    tmc    mmu
       cha    tmr    lru

   These unprotected special-purpose register names are also recognized:
       ipc    alu    fpe
       ipa    bp     inte
       ipb    fc     fps
       q      cr     exop

Floating Point
--------------

   The AMD 29K family uses IEEE floating-point numbers.

AMD 29K Machine Directives
--------------------------

`.block SIZE , FILL'
     This directive emits SIZE bytes, each of value FILL.  Both SIZE
     and FILL are absolute expressions.  If the comma and FILL are
     omitted, FILL is assumed to be zero.

     In other versions of the GNU assembler, this directive is called
     `.space'.

`.cputype'
     This directive is ignored; it is accepted for compatibility with
     other AMD 29K assemblers.

`.file'
     This directive is ignored; it is accepted for compatibility with
     other AMD 29K assemblers.

          *Warning:* in other versions of the GNU assembler, `.file' is
          used for the directive called `.app-file' in the AMD 29K
          support.

`.line'
     This directive is ignored; it is accepted for compatibility with
     other AMD 29K assemblers.

`.sect'
     This directive is ignored; it is accepted for compatibility with
     other AMD 29K assemblers.

`.use SECTION NAME'
     Establishes the section and subsection for the following code;
     SECTION NAME may be one of `.text', `.data', `.data1', or `.lit'.
     With one of the first three SECTION NAME options, `.use' is
     equivalent to the machine directive SECTION NAME; the remaining
     case, `.use .lit', is the same as `.data 200'.

Opcodes
-------

   `as' implements all the standard AMD 29K opcodes.  No additional
pseudo-instructions are needed on this family.

   For information on the 29K machine instruction set, see `Am29000
User's Manual', Advanced Micro Devices, Inc.

H8/300 Dependent Features
=========================

Options
-------

   `as' has no additional command-line options for the Hitachi H8/300
family.

Syntax
------

Special Characters
..................

   `;' is the line comment character.

   `$' can be used instead of a newline to separate statements.
Therefore *you may not use `$' in symbol names* on the H8/300.

Register Names
..............

   You can use predefined symbols of the form `rNh' and `rNl' to refer
to the H8/300 registers as sixteen 8-bit general-purpose registers.  N
is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are
valid register names.

   You can also use the eight predefined symbols `rN' to refer to the
H8/300 registers as 16-bit registers (you must use this form for
addressing).

   On the H8/300H, you can also use the eight predefined symbols `erN'
(`er0' ... `er7') to refer to the 32-bit general purpose registers.

   The two control registers are called `pc' (program counter; a 16-bit
register, except on the H8/300H where it is 24 bits) and `ccr'
(condition code register; an 8-bit register).  `r7' is used as the
stack pointer, and can also be called `sp'.

Addressing Modes
................

   as understands the following addressing modes for the H8/300:
`rN'
     Register direct

`@rN'
     Register indirect

`@(D, rN)'
`@(D:16, rN)'
`@(D:24, rN)'
     Register indirect: 16-bit or 24-bit displacement D from register
     N.  (24-bit displacements are only meaningful on the H8/300H.)

`@rN+'
     Register indirect with post-increment

`@-rN'
     Register indirect with pre-decrement

``@'AA'
``@'AA:8'
``@'AA:16'
``@'AA:24'
     Absolute address `aa'.  (The address size `:24' only makes sense
     on the H8/300H.)

`#XX'
`#XX:8'
`#XX:16'
`#XX:32'
     Immediate data XX.  You may specify the `:8', `:16', or `:32' for
     clarity, if you wish; but `as' neither requires this nor uses
     it--the data size required is taken from context.

``@'`@'AA'
``@'`@'AA:8'
     Memory indirect.  You may specify the `:8' for clarity, if you
     wish; but `as' neither requires this nor uses it.

Floating Point
--------------

   The H8/300 family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.

H8/300 Machine Directives
-------------------------

   `as' has only one machine-dependent directive for the H8/300:

`.h300h'
     Recognize and emit additional instructions for the H8/300H
     variant, and also make `.int' emit 32-bit numbers rather than the
     usual (16-bit) for the H8/300 family.

   On the H8/300 family (including the H8/300H) `.word' directives
generate 16-bit numbers.

Opcodes
-------

   For detailed information on the H8/300 machine instruction set, see
`H8/300 Series Programming Manual' (Hitachi ADE-602-025).  For
information specific to the H8/300H, see `H8/300H Series Programming
Manual' (Hitachi).

   `as' implements all the standard H8/300 opcodes.  No additional
pseudo-instructions are needed on this family.

   The following table summarizes the H8/300 opcodes, and their
arguments.  Entries marked `*' are opcodes used only on the H8/300H.

              Legend:
                 Rs   source register
                 Rd   destination register
                 abs  absolute address
                 imm  immediate data
              disp:N  N-bit displacement from a register
             pcrel:N  N-bit displacement relative to program counter

        add.b #imm,rd              *  andc #imm,ccr
        add.b rs,rd                   band #imm,rd
        add.w rs,rd                   band #imm,@rd
     *  add.w #imm,rd                 band #imm,@abs:8
     *  add.l rs,rd                   bra  pcrel:8
     *  add.l #imm,rd              *  bra  pcrel:16
        adds #imm,rd                  bt   pcrel:8
        addx #imm,rd               *  bt   pcrel:16
        addx rs,rd                    brn  pcrel:8
        and.b #imm,rd              *  brn  pcrel:16
        and.b rs,rd                   bf   pcrel:8
     *  and.w rs,rd                *  bf   pcrel:16
     *  and.w #imm,rd                 bhi  pcrel:8
     *  and.l #imm,rd              *  bhi  pcrel:16
     *  and.l rs,rd                   bls  pcrel:8

     *  bls  pcrel:16                 bld  #imm,rd
        bcc  pcrel:8                  bld  #imm,@rd
     *  bcc  pcrel:16                 bld  #imm,@abs:8
        bhs  pcrel:8                  bnot #imm,rd
     *  bhs  pcrel:16                 bnot #imm,@rd
        bcs  pcrel:8                  bnot #imm,@abs:8
     *  bcs  pcrel:16                 bnot rs,rd
        blo  pcrel:8                  bnot rs,@rd
     *  blo  pcrel:16                 bnot rs,@abs:8
        bne  pcrel:8                  bor  #imm,rd
     *  bne  pcrel:16                 bor  #imm,@rd
        beq  pcrel:8                  bor  #imm,@abs:8
     *  beq  pcrel:16                 bset #imm,rd
        bvc  pcrel:8                  bset #imm,@rd
     *  bvc  pcrel:16                 bset #imm,@abs:8
        bvs  pcrel:8                  bset rs,rd
     *  bvs  pcrel:16                 bset rs,@rd
        bpl  pcrel:8                  bset rs,@abs:8
     *  bpl  pcrel:16                 bsr  pcrel:8
        bmi  pcrel:8                  bsr  pcrel:16
     *  bmi  pcrel:16                 bst  #imm,rd
        bge  pcrel:8                  bst  #imm,@rd
     *  bge  pcrel:16                 bst  #imm,@abs:8
        blt  pcrel:8                  btst #imm,rd
     *  blt  pcrel:16                 btst #imm,@rd
        bgt  pcrel:8                  btst #imm,@abs:8
     *  bgt  pcrel:16                 btst rs,rd
        ble  pcrel:8                  btst rs,@rd
     *  ble  pcrel:16                 btst rs,@abs:8
        bclr #imm,rd                  bxor #imm,rd
        bclr #imm,@rd                 bxor #imm,@rd
        bclr #imm,@abs:8              bxor #imm,@abs:8
        bclr rs,rd                    cmp.b #imm,rd
        bclr rs,@rd                   cmp.b rs,rd
        bclr rs,@abs:8                cmp.w rs,rd
        biand #imm,rd                 cmp.w rs,rd
        biand #imm,@rd             *  cmp.w #imm,rd
        biand #imm,@abs:8          *  cmp.l #imm,rd
        bild #imm,rd               *  cmp.l rs,rd
        bild #imm,@rd                 daa  rs
        bild #imm,@abs:8              das  rs
        bior #imm,rd                  dec.b rs
        bior #imm,@rd              *  dec.w #imm,rd
        bior #imm,@abs:8           *  dec.l #imm,rd
        bist #imm,rd                  divxu.b rs,rd
        bist #imm,@rd              *  divxu.w rs,rd
        bist #imm,@abs:8           *  divxs.b rs,rd
        bixor #imm,rd              *  divxs.w rs,rd
        bixor #imm,@rd                eepmov
        bixor #imm,@abs:8          *  eepmovw

     *  exts.w rd                     mov.w rs,@abs:16
     *  exts.l rd                  *  mov.l #imm,rd
     *  extu.w rd                  *  mov.l rs,rd
     *  extu.l rd                  *  mov.l @rs,rd
        inc  rs                    *  mov.l @(disp:16,rs),rd
     *  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
     *  inc.l #imm,rd              *  mov.l @rs+,rd
        jmp  @rs                   *  mov.l @abs:16,rd
        jmp  abs                   *  mov.l @abs:24,rd
        jmp  @@abs:8               *  mov.l rs,@rd
        jsr  @rs                   *  mov.l rs,@(disp:16,rd)
        jsr  abs                   *  mov.l rs,@(disp:24,rd)
        jsr  @@abs:8               *  mov.l rs,@-rd
        ldc  #imm,ccr              *  mov.l rs,@abs:16
        ldc  rs,ccr                *  mov.l rs,@abs:24
     *  ldc  @abs:16,ccr              movfpe @abs:16,rd
     *  ldc  @abs:24,ccr              movtpe rs,@abs:16
     *  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
     *  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
     *  ldc  @rs+,ccr              *  mulxs.b rs,rd
     *  ldc  @rs,ccr               *  mulxs.w rs,rd
     *  mov.b @(disp:24,rs),rd        neg.b rs
     *  mov.b rs,@(disp:24,rd)     *  neg.w rs
        mov.b @abs:16,rd           *  neg.l rs
        mov.b rs,rd                   nop
        mov.b @abs:8,rd               not.b rs
        mov.b rs,@abs:8            *  not.w rs
        mov.b rs,rd                *  not.l rs
        mov.b #imm,rd                 or.b #imm,rd
        mov.b @rs,rd                  or.b rs,rd
        mov.b @(disp:16,rs),rd     *  or.w #imm,rd
        mov.b @rs+,rd              *  or.w rs,rd
        mov.b @abs:8,rd            *  or.l #imm,rd
        mov.b rs,@rd               *  or.l rs,rd
        mov.b rs,@(disp:16,rd)        orc  #imm,ccr
        mov.b rs,@-rd                 pop.w rs
        mov.b rs,@abs:8            *  pop.l rs
        mov.w rs,@rd                  push.w rs
     *  mov.w @(disp:24,rs),rd     *  push.l rs
     *  mov.w rs,@(disp:24,rd)        rotl.b rs
     *  mov.w @abs:24,rd           *  rotl.w rs
     *  mov.w rs,@abs:24           *  rotl.l rs
        mov.w rs,rd                   rotr.b rs
        mov.w #imm,rd              *  rotr.w rs
        mov.w @rs,rd               *  rotr.l rs
        mov.w @(disp:16,rs),rd        rotxl.b rs
        mov.w @rs+,rd              *  rotxl.w rs
        mov.w @abs:16,rd           *  rotxl.l rs
        mov.w rs,@(disp:16,rd)        rotxr.b rs
        mov.w rs,@-rd              *  rotxr.w rs

     *  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
        bpt                        *  stc  ccr,@-rd
        rte                        *  stc  ccr,@abs:16
        rts                        *  stc  ccr,@abs:24
        shal.b rs                     sub.b rs,rd
     *  shal.w rs                     sub.w rs,rd
     *  shal.l rs                  *  sub.w #imm,rd
        shar.b rs                  *  sub.l rs,rd
     *  shar.w rs                  *  sub.l #imm,rd
     *  shar.l rs                     subs #imm,rd
        shll.b rs                     subx #imm,rd
     *  shll.w rs                     subx rs,rd
     *  shll.l rs                  *  trapa #imm
        shlr.b rs                     xor  #imm,rd
     *  shlr.w rs                     xor  rs,rd
     *  shlr.l rs                  *  xor.w #imm,rd
        sleep                      *  xor.w rs,rd
        stc  ccr,rd                *  xor.l #imm,rd
     *  stc  ccr,@rs               *  xor.l rs,rd
     *  stc  ccr,@(disp:16,rd)        xorc #imm,ccr

   Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
with variants using the suffixes `.b', `.w', and `.l' to specify the
size of a memory operand.  `as' supports these suffixes, but does not
require them; since one of the operands is always a register, `as' can
deduce the correct size.

   For example, since `r0' refers to a 16-bit register,
     mov    r0,@foo
is equivalent to
     mov.w  r0,@foo

   If you use the size suffixes, `as' issues a warning when the suffix
and the register size do not match.

H8/500 Dependent Features
=========================

Options
-------

   `as' has no additional command-line options for the Hitachi H8/500
family.

Syntax
------

Special Characters
..................

   `!' is the line comment character.

   `;' can be used instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.

Register Names
..............

   You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', and `r7' to refer to the H8/500 registers.

   The H8/500 also has these control registers:

`cp'
     code pointer

`dp'
     data pointer

`bp'
     base pointer

`tp'
     stack top pointer

`ep'
     extra pointer

`sr'
     status register

`ccr'
     condition code register

   All registers are 16 bits long.  To represent 32 bit numbers, use two
adjacent registers; for distant memory addresses, use one of the segment
pointers (`cp' for the program counter; `dp' for `r0'-`r3'; `ep' for
`r4' and `r5'; and `tp' for `r6' and `r7'.

Addressing Modes
................

   as understands the following addressing modes for the H8/500:
`RN'
     Register direct

`@RN'
     Register indirect

`@(d:8, RN)'
     Register indirect with 8 bit signed displacement

`@(d:16, RN)'
     Register indirect with 16 bit signed displacement

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@AA:8'
     8 bit absolute address

`@AA:16'
     16 bit absolute address

`#XX:8'
     8 bit immediate

`#XX:16'
     16 bit immediate

Floating Point
--------------

   The H8/500 family uses IEEE floating-point numbers.

H8/500 Machine Directives
-------------------------

   `as' has no machine-dependent directives for the H8/500.  However,
on this platform the `.int' and `.word' directives generate 16-bit
numbers.

Opcodes
-------

   For detailed information on the H8/500 machine instruction set, see
`H8/500 Series Programming Manual' (Hitachi M21T001).

   `as' implements all the standard H8/500 opcodes.  No additional
pseudo-instructions are needed on this family.

   The following table summarizes H8/500 opcodes and their operands:

     Legend:
     abs8      8-bit absolute address
     abs16     16-bit absolute address
     abs24     24-bit absolute address
     crb       `ccr', `br', `ep', `dp', `tp', `dp'
     disp8     8-bit displacement
     ea        `rn', `@rn', `@(d:8, rn)', `@(d:16, rn)',
               `@-rn', `@rn+', `@aa:8', `@aa:16',
               `#xx:8', `#xx:16'
     ea_mem    `@rn', `@(d:8, rn)', `@(d:16, rn)',
               `@-rn', `@rn+', `@aa:8', `@aa:16'
     ea_noimm  `rn', `@rn', `@(d:8, rn)', `@(d:16, rn)',
               `@-rn', `@rn+', `@aa:8', `@aa:16'
     fp        r6
     imm4      4-bit immediate data
     imm8      8-bit immediate data
     imm16     16-bit immediate data
     pcrel8    8-bit offset from program counter
     pcrel16   16-bit offset from program counter
     qim       `-2', `-1', `1', `2'
     rd        any register
     rs        a register distinct from rd
     rlist     comma-separated list of registers in parentheses;
               register ranges `rd-rs' are allowed
     sp        stack pointer (`r7')
     sr        status register
     sz        size; `.b' or `.w'.  If omitted, default `.w'

     ldc[.b] ea,crb                 bcc[.w] pcrel16
     ldc[.w] ea,sr                  bcc[.b] pcrel8
     add[:q] sz qim,ea_noimm        bhs[.w] pcrel16
     add[:g] sz ea,rd               bhs[.b] pcrel8
     adds sz ea,rd                  bcs[.w] pcrel16
     addx sz ea,rd                  bcs[.b] pcrel8
     and sz ea,rd                   blo[.w] pcrel16
     andc[.b] imm8,crb              blo[.b] pcrel8
     andc[.w] imm16,sr              bne[.w] pcrel16
     bpt                            bne[.b] pcrel8
     bra[.w] pcrel16                beq[.w] pcrel16
     bra[.b] pcrel8                 beq[.b] pcrel8
     bt[.w] pcrel16                 bvc[.w] pcrel16
     bt[.b] pcrel8                  bvc[.b] pcrel8
     brn[.w] pcrel16                bvs[.w] pcrel16
     brn[.b] pcrel8                 bvs[.b] pcrel8
     bf[.w] pcrel16                 bpl[.w] pcrel16
     bf[.b] pcrel8                  bpl[.b] pcrel8
     bhi[.w] pcrel16                bmi[.w] pcrel16
     bhi[.b] pcrel8                 bmi[.b] pcrel8
     bls[.w] pcrel16                bge[.w] pcrel16
     bls[.b] pcrel8                 bge[.b] pcrel8

     blt[.w] pcrel16                mov[:g][.b] imm8,ea_mem
     blt[.b] pcrel8                 mov[:g][.w] imm16,ea_mem
     bgt[.w] pcrel16                movfpe[.b] ea,rd
     bgt[.b] pcrel8                 movtpe[.b] rs,ea_noimm
     ble[.w] pcrel16                mulxu sz ea,rd
     ble[.b] pcrel8                 neg sz ea
     bclr sz imm4,ea_noimm          nop
     bclr sz rs,ea_noimm            not sz ea
     bnot sz imm4,ea_noimm          or sz ea,rd
     bnot sz rs,ea_noimm            orc[.b] imm8,crb
     bset sz imm4,ea_noimm          orc[.w] imm16,sr
     bset sz rs,ea_noimm            pjmp abs24
     bsr[.b] pcrel8                 pjmp @rd
     bsr[.w] pcrel16                pjsr abs24
     btst sz imm4,ea_noimm          pjsr @rd
     btst sz rs,ea_noimm            prtd imm8
     clr sz ea                      prtd imm16
     cmp[:e][.b] imm8,rd            prts
     cmp[:i][.w] imm16,rd           rotl sz ea
     cmp[:g].b imm8,ea_noimm        rotr sz ea
     cmp[:g][.w] imm16,ea_noimm     rotxl sz ea
     Cmp[:g] sz ea,rd               rotxr sz ea
     dadd rs,rd                     rtd imm8
     divxu sz ea,rd                 rtd imm16
     dsub rs,rd                     rts
     exts[.b] rd                    scb/f rs,pcrel8
     extu[.b] rd                    scb/ne rs,pcrel8
     jmp @rd                        scb/eq rs,pcrel8
     jmp @(imm8,rd)                 shal sz ea
     jmp @(imm16,rd)                shar sz ea
     jmp abs16                      shll sz ea
     jsr @rd                        shlr sz ea
     jsr @(imm8,rd)                 sleep
     jsr @(imm16,rd)                stc[.b] crb,ea_noimm
     jsr abs16                      stc[.w] sr,ea_noimm
     ldm @sp+,(rlist)               stm (rlist),@-sp
     link fp,imm8                   sub sz ea,rd
     link fp,imm16                  subs sz ea,rd
     mov[:e][.b] imm8,rd            subx sz ea,rd
     mov[:i][.w] imm16,rd           swap[.b] rd
     mov[:l][.w] abs8,rd            tas[.b] ea
     mov[:l].b abs8,rd              trapa imm4
     mov[:s][.w] rs,abs8            trap/vs
     mov[:s].b rs,abs8              tst sz ea
     mov[:f][.w] @(disp8,fp),rd     unlk fp
     mov[:f][.w] rs,@(disp8,fp)     xch[.w] rs,rd
     mov[:f].b @(disp8,fp),rd       xor sz ea,rd
     mov[:f].b rs,@(disp8,fp)       xorc.b imm8,crb
     mov[:g] sz rs,ea_mem           xorc.w imm16,sr
     mov[:g] sz ea,rd

Hitachi SH Dependent Features
=============================

Options
-------

   `as' has no additional command-line options for the Hitachi SH
family.

Syntax
------

Special Characters
..................

   `!' is the line comment character.

   You can use `;' instead of a newline to separate statements.

   Since `$' has no special meaning, you may use it in symbol names.

Register Names
..............

   You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and
`r15' to refer to the SH registers.

   The SH also has these control registers:

`pr'
     procedure register (holds return address)

`pc'
     program counter

`mach'
`macl'
     high and low multiply accumulator registers

`sr'
     status register

`gbr'
     global base register

`vbr'
     vector base register (for interrupt vectors)

Addressing Modes
................

   `as' understands the following addressing modes for the SH.  `RN' in
the following refers to any of the numbered registers, but *not* the
control registers.

`RN'
     Register direct

`@RN'
     Register indirect

`@-RN'
     Register indirect with pre-decrement

`@RN+'
     Register indirect with post-increment

`@(DISP, RN)'
     Register indirect with displacement

`@(R0, RN)'
     Register indexed

`@(DISP, GBR)'
     `GBR' offset

`@(R0, GBR)'
     GBR indexed

`ADDR'
`@(DISP, PC)'
     PC relative address (for branch or for addressing memory).  The
     `as' implementation allows you to use the simpler form ADDR
     anywhere a PC relative address is called for; the alternate form
     is supported for compatibility with other assemblers.

`#IMM'
     Immediate data

Floating Point
--------------

   The SH family uses IEEE floating-point numbers.

SH Machine Directives
---------------------

   `as' has no machine-dependent directives for the SH.

Opcodes
-------

   For detailed information on the SH machine instruction set, see
`SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).

   `as' implements all the standard SH opcodes.  No additional
pseudo-instructions are needed on this family.  Note, however, that
because `as' supports a simpler form of PC-relative addressing, you may
simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar'
from the program counter:

     mov.l  @(DISP, PC)

   Here is a summary of SH opcodes:

     Legend:
     Rn        a numbered register
     Rm        another numbered register
     #imm      immediate data
     disp      displacement
     disp8     8-bit displacement
     disp12    12-bit displacement

     add #imm,Rn                    lds.l @Rn+,PR
     add Rm,Rn                      mac.w @Rm+,@Rn+
     addc Rm,Rn                     mov #imm,Rn
     addv Rm,Rn                     mov Rm,Rn
     and #imm,R0                    mov.b Rm,@(R0,Rn)
     and Rm,Rn                      mov.b Rm,@-Rn
     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
     bf disp8                       mov.b @(disp,Rm),R0
     bra disp12                     mov.b @(disp,GBR),R0
     bsr disp12                     mov.b @(R0,Rm),Rn
     bt disp8                       mov.b @Rm+,Rn
     clrm                           mov.b @Rm,Rn
     clrt                           mov.b R0,@(disp,Rm)
     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
     cmp/hi Rm,Rn                   mov.l Rm,@Rn
     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
     cmp/pl Rn                      mov.l @(disp,GBR),R0
     cmp/pz Rn                      mov.l @(disp,PC),Rn
     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
     div0s Rm,Rn                    mov.l @Rm+,Rn
     div0u                          mov.l @Rm,Rn
     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
     exts.w Rm,Rn                   mov.w Rm,@-Rn
     extu.b Rm,Rn                   mov.w Rm,@Rn
     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
     jmp @Rn                        mov.w @(disp,GBR),R0
     jsr @Rn                        mov.w @(disp,PC),Rn
     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
     ldc Rn,SR                      mov.w @Rm+,Rn
     ldc Rn,VBR                     mov.w @Rm,Rn
     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
     lds Rn,MACH                    movt Rn
     lds Rn,MACL                    muls Rm,Rn
     lds Rn,PR                      mulu Rm,Rn
     lds.l @Rn+,MACH                neg Rm,Rn
     lds.l @Rn+,MACL                negc Rm,Rn

     nop                            stc VBR,Rn
     not Rm,Rn                      stc.l GBR,@-Rn
     or #imm,R0                     stc.l SR,@-Rn
     or Rm,Rn                       stc.l VBR,@-Rn
     or.b #imm,@(R0,GBR)            sts MACH,Rn
     rotcl Rn                       sts MACL,Rn
     rotcr Rn                       sts PR,Rn
     rotl Rn                        sts.l MACH,@-Rn
     rotr Rn                        sts.l MACL,@-Rn
     rte                            sts.l PR,@-Rn
     rts                            sub Rm,Rn
     sett                           subc Rm,Rn
     shal Rn                        subv Rm,Rn
     shar Rn                        swap.b Rm,Rn
     shll Rn                        swap.w Rm,Rn
     shll16 Rn                      tas.b @Rn
     shll2 Rn                       trapa #imm
     shll8 Rn                       tst #imm,R0
     shlr Rn                        tst Rm,Rn
     shlr16 Rn                      tst.b #imm,@(R0,GBR)
     shlr2 Rn                       xor #imm,R0
     shlr8 Rn                       xor Rm,Rn
     sleep                          xor.b #imm,@(R0,GBR)
     stc GBR,Rn                     xtrct Rm,Rn
     stc SR,Rn

Intel 80960 Dependent Features
==============================

i960 Command-line Options
-------------------------

`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
     Select the 80960 architecture.  Instructions or features not
     supported by the selected architecture cause fatal errors.

     `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
     Synonyms are provided for compatibility with other tools.

     If none of these options is specified, `as' will generate code for
     any instruction or feature that is supported by *some* version of
     the 960 (even if this means mixing architectures!).  In principle,
     `as' will attempt to deduce the minimal sufficient processor type
     if none is specified; depending on the object code format, the
     processor type may be recorded in the object file.  If it is
     critical that the `as' output match a specific architecture,
     specify that architecture explicitly.

`-b'
     Add code to collect information about conditional branches taken,
     for later optimization using branch prediction bits.  (The
     conditional branch instructions have branch prediction bits in the
     CA, CB, and CC architectures.)  If BR represents a conditional
     branch instruction, the following represents the code generated by
     the assembler when `-b' is specified:

                  call    INCREMENT ROUTINE
                  .word   0       # pre-counter
          Label:  BR
                  call    INCREMENT ROUTINE
                  .word   0       # post-counter

     The counter following a branch records the number of times that
     branch was *not* taken; the differenc between the two counters is
     the number of times the branch *was* taken.

     A table of every such `Label' is also generated, so that the
     external postprocessor `gbr960' (supplied by Intel) can locate all
     the counters.  This table is always labelled `__BRANCH_TABLE__';
     this is a local symbol to permit collecting statistics for many
     separate object files.  The table is word aligned, and begins with
     a two-word header.  The first word, initialized to 0, is used in
     maintaining linked lists of branch tables.  The second word is a
     count of the number of entries in the table, which follow
     immediately: each is a word, pointing to one of the labels
     illustrated above.

           +------------+------------+------------+ ... +------------+
           |            |            |            |     |            |
           |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
           |            |            |            |     |            |
           +------------+------------+------------+ ... +------------+

                         __BRANCH_TABLE__ layout

     The first word of the header is used to locate multiple branch
     tables, since each object file may contain one. Normally the links
     are maintained with a call to an initialization routine, placed at
     the beginning of each function in the file.  The GNU C compiler
     will generate these calls automatically when you give it a `-b'
     option.  For further details, see the documentation of `gbr960'.

`-norelax'
     Normally, Compare-and-Branch instructions with targets that require
     displacements greater than 13 bits (or that have external targets)
     are replaced with the corresponding compare (or `chkbit') and
     branch instructions.  You can use the `-norelax' option to specify
     that `as' should generate errors instead, if the target
     displacement is larger than 13 bits.

     This option does not affect the Compare-and-Jump instructions; the
     code emitted for them is *always* adjusted when necessary
     (depending on displacement size), regardless of whether you use
     `-norelax'.

Floating Point
--------------

   `as' generates IEEE floating-point numbers for the directives
`.float', `.double', `.extended', and `.single'.

i960 Machine Directives
-----------------------

`.bss SYMBOL, LENGTH, ALIGN'
     Reserve LENGTH bytes in the bss section for a local SYMBOL,
     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
     must be positive absolute expressions.  This directive differs
     from `.lcomm' only in that it permits you to specify an alignment.
     See `.lcomm'.

`.extended FLONUMS'
     `.extended' expects zero or more flonums, separated by commas; for
     each flonum, `.extended' emits an IEEE extended-format (80-bit)
     floating-point number.

`.leafproc CALL-LAB, BAL-LAB'
     You can use the `.leafproc' directive in conjunction with the
     optimized `callj' instruction to enable faster calls of leaf
     procedures.  If a procedure is known to call no other procedures,
     you may define an entry point that skips procedure prolog code
     (and that does not depend on system-supplied saved context), and
     declare it as the BAL-LAB using `.leafproc'.  If the procedure
     also has an entry point that goes through the normal prolog, you
     can specify that entry point as CALL-LAB.

     A `.leafproc' declaration is meant for use in conjunction with the
     optimized call instruction `callj'; the directive records the data
     needed later to choose between converting the `callj' into a `bal'
     or a `call'.

     CALL-LAB is optional; if only one argument is present, or if the
     two arguments are identical, the single argument is assumed to be
     the `bal' entry point.

`.sysproc NAME, INDEX'
     The `.sysproc' directive defines a name for a system procedure.
     After you define it using `.sysproc', you can use NAME to refer to
     the system procedure identified by INDEX when calling procedures
     with the optimized call instruction `callj'.

     Both arguments are required; INDEX must be between 0 and 31
     (inclusive).

i960 Opcodes
------------

   All Intel 960 machine instructions are supported; see i960 Command-line Options
for a discussion of selecting the
instruction subset for a particular 960 architecture.

   Some opcodes are processed beyond simply emitting a single
corresponding instruction: `callj', and Compare-and-Branch or
Compare-and-Jump instructions with target displacements larger than 13
bits.

`callj'
.......

   You can write `callj' to have the assembler or the linker determine
the most appropriate form of subroutine call: `call', `bal', or
`calls'.  If the assembly source contains enough information--a
`.leafproc' or `.sysproc' directive defining the operand--then `as'
will translate the `callj'; if not, it will simply emit the `callj',
leaving it for the linker to resolve.

Compare-and-Branch
..................

   The 960 architectures provide combined Compare-and-Branch
instructions that permit you to store the branch target in the lower 13
bits of the instruction word itself.  However, if you specify a branch
target far enough away that its address won't fit in 13 bits, the
assembler can either issue an error, or convert your Compare-and-Branch
instruction into separate instructions to do the compare and the branch.

   Whether `as' gives an error or expands the instruction depends on
two choices you can make: whether you use the `-norelax' option, and
whether you use a "Compare and Branch" instruction or a "Compare and
Jump" instruction.  The "Jump" instructions are *always* expanded if
necessary; the "Branch" instructions are expanded when necessary
*unless* you specify `-norelax'--in which case `as' gives an error
instead.

   These are the Compare-and-Branch instructions, their "Jump" variants,
and the instruction pairs they may expand into:

             Compare and
          Branch      Jump       Expanded to
          ------    ------       ------------
             bbc                 chkbit; bno
             bbs                 chkbit; bo
          cmpibe    cmpije       cmpi; be
          cmpibg    cmpijg       cmpi; bg
         cmpibge   cmpijge       cmpi; bge
          cmpibl    cmpijl       cmpi; bl
         cmpible   cmpijle       cmpi; ble
         cmpibno   cmpijno       cmpi; bno
         cmpibne   cmpijne       cmpi; bne
          cmpibo    cmpijo       cmpi; bo
          cmpobe    cmpoje       cmpo; be
          cmpobg    cmpojg       cmpo; bg
         cmpobge   cmpojge       cmpo; bge
          cmpobl    cmpojl       cmpo; bl
         cmpoble   cmpojle       cmpo; ble
         cmpobne   cmpojne       cmpo; bne

M680x0 Dependent Features
=========================

M680x0 Options
--------------

   The Motorola 680x0 version of `as' has two machine dependent options.
One shortens undefined references from 32 to 16 bits, while the other
is used to tell `as' what kind of machine it is assembling for.

   You can use the `-l' option to shorten the size of references to
undefined symbols.  If the `-l' option is not given, references to
undefined symbols will be a full long (32 bits) wide.  (Since `as'
cannot know where these symbols will end up, `as' can only allocate
space for the linker to fill in later.  Since `as' doesn't know how far
away these symbols will be, it allocates as much space as it can.) If
this option is given, the references will only be one word wide (16
bits).  This may be useful if you want the object file to be as small as
possible, and you know that the relevant symbols will be less than 17
bits away.

   The 680x0 version of `as' is most frequently used to assemble
programs for the Motorola MC68020 microprocessor.  Occasionally it is
used to assemble programs for the mostly similar, but slightly different
MC68000 or MC68010 microprocessors.  You can give `as' the options
`-m68000', `-mc68000', `-m68010', `-mc68010', `-m68020', and `-mc68020'
to tell it what processor is the target.

Syntax
------

   This syntax for the Motorola 680x0 was developed at MIT.

   The 680x0 version of `as' uses syntax similar to the Sun assembler.
Intervening periods are now ignored; for example, `movl' is equivalent
to `move.l'.

   In the following table "apc" stands for any of the address registers
(`a0' through `a7'), nothing, (`'), the Program Counter (`pc'), or the
zero-address relative to the program counter (`zpc').

   The following addressing modes are understood:
"Immediate"
     `#DIGITS'

"Data Register"
     `d0' through `d7'

"Address Register"
     `a0' through `a7'

"Address Register Indirect"
     `a0@' through `a7@'
     `a7' is also known as `sp', i.e. the Stack Pointer.  `a6' is also
     known as `fp', the Frame Pointer.

"Address Register Postincrement"
     `a0@+' through `a7@+'

"Address Register Predecrement"
     `a0@-' through `a7@-'

"Indirect Plus Offset"
     `APC@(DIGITS)'

"Index"
     `APC@(DIGITS,REGISTER:SIZE:SCALE)'

     or `APC@(REGISTER:SIZE:SCALE)'

"Postindex"
     `APC@(DIGITS)@(DIGITS,REGISTER:SIZE:SCALE)'

     or `APC@(DIGITS)@(REGISTER:SIZE:SCALE)'

"Preindex"
     `APC@(DIGITS,REGISTER:SIZE:SCALE)@(DIGITS)'

     or `APC@(REGISTER:SIZE:SCALE)@(DIGITS)'

"Memory Indirect"
     `APC@(DIGITS)@(DIGITS)'

"Absolute"
     `SYMBOL', or `DIGITS'

   For some configurations, especially those where the compiler normally
does not prepend an underscore to the names of user variables, the
assembler requires a `%' before any use of a register name.  This is
intended to let the assembler distinguish between user variables and
registers named `a0' through `a7', et cetera.  The `%' is always
accepted, but is only required for some configurations, notably
`m68k-coff'.

Motorola Syntax
---------------

   The standard Motorola syntax for this chip differs from the syntax
already discussed (see Syntax).  `as' can accept both
kinds of syntax, even within a single instruction.  The syntaxes are
fully compatible, because the Motorola syntax never uses the `@'
character and the MIT syntax always does, except in cases where the
syntaxes are identical.

   In particular, you may write or generate M68K assembler with the
following conventions:

   (In the following table "apc" stands for any of the address
registers (`a0' through `a7'), nothing, (`'), the Program Counter
(`pc'), or the zero-address relative to the program counter (`zpc').)

   The following additional addressing modes are understood:
"Address Register Indirect"
     `a0' through `a7'
     `a7' is also known as `sp', i.e. the Stack Pointer.  `a6' is also
     known as `fp', the Frame Pointer.

"Address Register Postincrement"
     `(a0)+' through `(a7)+'

"Address Register Predecrement"
     `-(a0)' through `-(a7)'

"Indirect Plus Offset"
     `DIGITS(APC)'

"Index"
     `DIGITS(APC,(REGISTER.SIZE*SCALE)'
     or `(APC,REGISTER.SIZE*SCALE)'
     In either case, SIZE and SCALE are optional (SCALE defaults to
     `1', SIZE defaults to `l').   SCALE can be `1', `2', `4', or `8'.
     SIZE can be `w' or `l'.  SCALE is only supported on the 68020 and
     greater.

Floating Point
--------------

   The floating point code is not too well tested, and may have subtle
bugs in it.

   Packed decimal (P) format floating literals are not supported.  Feel
free to add the code!

   The floating point formats generated by directives are these.

`.float'
     `Single' precision floating point constants.

`.double'
     `Double' precision floating point constants.

   There is no directive to produce regions of memory holding extended
precision numbers, however they can be used as immediate operands to
floating-point instructions.  Adding a directive to create extended
precision numbers would not be hard, but it has not yet seemed
necessary.

680x0 Machine Directives
------------------------

   In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.

`.data1'
     This directive is identical to a `.data 1' directive.

`.data2'
     This directive is identical to a `.data 2' directive.

`.even'
     This directive is identical to a `.align 1' directive.

`.skip'
     This directive is identical to a `.space' directive.

Opcodes
-------

Branch Improvement
..................

   Certain pseudo opcodes are permitted for branch instructions.  They
expand to the shortest branch instruction that will reach the target.
Generally these mnemonics are made by substituting `j' for `b' at the
start of a Motorola mnemonic.

   The following table summarizes the pseudo-operations.  A `*' flags
cases that are more fully described after the table:

               Displacement
               +-------------------------------------------------
               |                68020   68000/10
     Pseudo-Op |BYTE    WORD    LONG    LONG      non-PC relative
               +-------------------------------------------------
          jbsr |bsrs    bsr     bsrl    jsr       jsr
           jra |bras    bra     bral    jmp       jmp
     *     jXX |bXXs    bXX     bXXl    bNXs;jmpl bNXs;jmp
     *    dbXX |dbXX    dbXX        dbXX; bra; jmpl
     *    fjXX |fbXXw   fbXXw   fbXXl             fbNXw;jmp

     XX: condition
     NX: negative of condition XX

                    `*'--see full description below

`jbsr'
`jra'
     These are the simplest jump pseudo-operations; they always map to
     one particular machine instruction, depending on the displacement
     to the branch target.

`jXX'
     Here, `jXX' stands for an entire family of pseudo-operations,
     where XX is a conditional branch or condition-code test.  The full
     list of pseudo-ops in this family is:
           jhi   jls   jcc   jcs   jne   jeq   jvc
           jvs   jpl   jmi   jge   jlt   jgt   jle

     For the cases of non-PC relative displacements and long
     displacements on the 68000 or 68010, `as' will issue a longer code
     fragment in terms of NX, the opposite condition to XX.  For
     example, for the non-PC relative case:
              jXX foo
     gives
               bNXs oof
               jmp foo
           oof:

`dbXX'
     The full family of pseudo-operations covered here is
           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
           dbf    dbra   dbt

     Other than for word and byte displacements, when the source reads
     `dbXX foo', `as' will emit
               dbXX oo1
               bra oo2
           oo1:jmpl foo
           oo2:

`fjXX'
     This family includes
           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
           fjugt  fjule  fjult  fjun

     For branch targets that are not PC relative, `as' emits
               fbNX oof
               jmp foo
           oof:
     when it encounters `fjXX foo'.